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Methods and apparatus are disclosed for generating and checking CRC values using a multi-byte CRC generator and a binary Galois field (“GF2”) multiplier. These methods and apparatus could be used in an unlimited number of applications and environments, such as part of computer or communications device (e.g., router or switch). The CRC generator and/or checker may be implemented singularly or in a combination of technologies, including, but not limited to, software, firmware, hardware, customized circuitry, application-specific integrated circuits, etc. A CRC generator is used to calculate a preliminary CRC value on a block of information. This CRC generator may be a balanced XOR tree or some other implementation, which calculates the preliminary CRC value on groups of n bytes of data at a time, where n is some integer greater than one. For example, when data is transferred over a 512 wide bit bus, typically the value of n would be 64 (i.e., 512 bits divided by 8 bits per byte).
Because the number of bytes in the data group may not be an even multiple of the value of n, one or more bytes of value zero may be appended to the data group to make it an even multiple, with the preliminary CRC being calculated on the entire appended data group. A GF2 multiplier uses the preliminary CRC value and the number of appended bytes of value zero to calculate the actual CRC value of the information. What is claimed is: 1. A method for determining a cyclic redundancy check (CRC) on a block of information, the method comprising: determining a preliminary CRC on the block of information plus at least one additional byte of information; and performing a binary Galois field (“GF2”) multiplier operation on the preliminary CRC to identify the CRC for the block of information. The method of claim 1, wherein the GF2 multiplier operation on the preliminary CRC includes selecting an operand based at least in part on the number of bytes in said at least one additional byte of information.
The method of claim 2, wherein the operand is selected from a plurality of operands maintained in a lookup table. The method of claim 1, wherein said performing the GF2 multiplier operation on the preliminary CRC includes selecting an operand to generate the CRC equivalent to the preliminary CRC. The method of claim 1, wherein the block of information includes a plurality of bytes; and wherein said determining the preliminary CRC includes simultaneously operating on the plurality of bytes. The method of claim 5, wherein said simultaneously operating the plurality of bytes includes an operation of a balanced XOR tree. The method of claim 5, wherein said determining the preliminary CRC includes operating on a single byte of block of information at a given time.
The method of claim 7, wherein said operating on the single byte of block of information at the given time includes an operation of a shift register. The method of claim 1, comprising receiving the block of information. The method of claim 1, wherein the preliminary CRC and the CRC are both CRC-32 cyclic redundancy codes. The method of claim 1, wherein the block of information includes a packet of information. The method of claim 11, wherein the packet of information includes fields of an Ethernet packet.
The method of claim 1, wherein the block of information includes a plurality of sets of bytes and a non-full set of bytes, and wherein said determining the preliminary CRC on the block of information plus at least one additional byte of information includes: initializing the preliminary CRC; determining the preliminary CRC on the plurality of sets of bytes; and determining the preliminary CRC on the non-full set of bytes plus said at least one additional byte of information. The method of claim 13, wherein said determining the preliminary CRC on the plurality of sets of bytes includes selecting an operand to generate the CRC equivalent to the preliminary CRC by a second GF2 multiplier operation.
The method of claim 13, wherein each of said at least one additional byte of information has a value of zero. The method of claim 15, wherein said performing the GF2 multiplier operation on the preliminary CRC includes selecting circuitry or a set of equations based on the number of bytes in said at least one additional byte of information. The method of claim 1, comprising comparing the determined CRC with an expected CRC value. The method of claim 17, further comprising generating a signal indicating a valid CRC if the determined CRC equals the expected CRC value. The method of claim 17, further comprising generating a signal indicating an invalid CRC if the determined CRC does not equal the expected CRC value.
The method of claim 1, wherein said at least one additional byte of information includes at least one byte having a value of zero. The method of claim 1, wherein each of said at least one additional byte of information has a value of zero. An apparatus for determining a cyclic redundancy check (CRC) on a block of information, the apparatus comprising: a preliminary CRC generator configured to generate a preliminary CRC based on the block of information; and a binary Galois field (“GF2”) multiplier, coupled to the preliminary CRC generator, configured to generate the CRC on the block of information based on the preliminary CRC. The apparatus of claim 22, further including a byte clearing mechanism for setting to zero a portion of a set of bytes operated on by the preliminary CRC generator. The apparatus of claim 22, including a selection mechanism for selecting circuitry based on a number of bytes set or not set to zero of the bytes operated on by the, preliminary CRC generator. The apparatus of claim 22, including a selection mechanism for selecting a set of operations based on a number of bytes set or not set to zero of the bytes operated on by the preliminary CRC generator. The apparatus of claim 22, wherein the preliminary CRC generator includes a balanced XOR tree.
An apparatus for determining a cyclic redundancy check (CRC) on a block of information, the apparatus comprising: means for determining a preliminary CRC value on the block of information combined with at least one additional byte of information; and means for determining the CRC from the preliminary CRC value using a binary Galois field (“GF2”) multiplier. The apparatus of claim 27, wherein the means for determining the CRC from the preliminary CRC value using the GF2 multiplier includes means for selecting circuitry or a set of operations based on the number of bytes in said at least one additional byte of information. A computer-readable medium containing computer-executable instructions for performing steps for determining a cyclic redundancy check (CRC) on a block of information, said steps comprising: determining a preliminary CRC on the block of information plus at least one additional byte of information; and performing a binary Galois field (“GF2”) multiplier operation on the preliminary CRC to identify the CRC for the block of information. The computer-readable medium of claim 29, wherein the GF2 multiplier operation on the preliminary CRC includes selecting an operand based at least in part on the number of bytes in said at least one additional byte of information. The computer-readable medium of claims 30, wherein the operand is selected from a plurality of operands maintained in a lookup table. The computer-readable medium of claim 29, wherein said performing the GF2 multiplier operation on the preliminary CRC includes selecting an operand to generate the CRC equivalent to the preliminary CRC.
The computer-readable medium of claim 29, wherein the block of information includes a plurality of bytes; and wherein said determining the preliminary CRC includes simultaneously operating on the plurality of bytes. The computer-readable medium of claim 33, wherein said simultaneously operating the plurality of bytes includes an operation of a balanced XOR tree. The computer-readable medium of claim 33, wherein said determining the preliminary CRC includes operating on a single byte of block of information at a given time. The computer-readable medium of claim 35, wherein said operating on the single byte of block of information at the given time includes an operation of a shift register. The computer-readable medium of claim 29, wherein the block of information includes a plurality of sets of bytes and a non-full set of bytes, and wherein said determining the preliminary CRC on the block of information plus at least one additional byte of information includes: initializing the preliminary CRC; determining the preliminary CRC on the plurality of sets of bytes; and determining the preliminary CRC on the non-full set of bytes plus said at least one additional byte of information. The computer-readable medium of claim 37, wherein said determining the preliminary CRC on the plurality of sets of bytes includes selecting an operand to generate the CRC equivalent to the preliminary CRC by a second GF2 multiplier operation.
The computer-readable medium of claim 37, wherein each of said at least one additional byte of information has a value of zero. The computer-readable medium of claim 39, wherein said performing the GF2 multiplier operation on the preliminary CRC includes selecting circuitry or a set of equations based on the number of bytes in said at least one additional byte of information. The computer-readable medium of claim 29, wherein said at least one additional byte of information includes at least one byte having a value of zero. The computer-readable medium of claim 29, wherein each of said at least one additional byte of information has a value of zero. FIELD OF THE INVENTION The invention relates to detecting errors in communication between components and/or systems; more particular, the invention relates to generating and checking cyclic redundancy code (CRC) values using a CRC generator and binary Galois field multiplier. BACKGROUND OF THE INVENTION Devices such as computers, routers, networking equipment, and components thereof communicate information internally and/or with other devices. For example, computers might communicate across a local area network (LAN) using Ethernet protocol, or application-specific integrated circuits (ASICs) may communicate with each other over a single or parallel bit bus.
It is important for these devices to reliably communicate and to detect errors in their communication. One common technique for detecting transmission errors is a technique known as the cyclic redundancy check (CRC).
A CRC allows the detection of errors using only a small number of redundant bits typically sent along with the communicated information. For example, a 32-bit CRC gives strong protection against common bit errors in messages that are thousands of bits long. Ethernet, a common link-level protocol, uses a frame format that includes CRC-32, a specific 32-bit CRC having the polynomial of: CRC-32: P( x)= x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x+1 One common method for computation of a CRC operates serially on each bit of a message using a shift register and XOR gates, where the number of bits in the shift register equals the degree of the CRC generating polynomial. The value of the CRC is determined by calculating the CRC from the first byte of the frame and stops calculating the CRC at the last byte. During transmission, this CRC is usually appended to the end of the frame. The receiver of the frame then calculates the CRC on the frame it receives, and compares the calculated CRC to the data source generated CRC that was appended to the end of the frame. If they match, the frame has a good CRC; otherwise, the frame is corrupted and is typically discarded.
This serial approach for determining a CRC may be sufficient for certain applications. However, especially at higher operating rates, the serial determination of a CRC may be too slow or may limit the effective communication rate between devices or components. One approach to increase the rate for determining a CRC is to process several bytes in parallel, such as using a balanced XOR tree.
However, a balanced XOR tree suffers from the inability to adjust to a variable number of bytes on which to determine a CRC. For example, Ethernet frames are of variable length from sixty-four bytes to 1518 bytes. Thus, a high-speed-device, such as a switch, transmitting Ethernet frames needs to accommodate the calculation of a CRC on frames of varying lengths. For example, if sixty-four bytes are operated on in parallel, then there are sixty-four possibilities where the last byte can be located. One costly approach to accommodate variable length data frames is to implement multiple, independent balanced XOR trees for each possible data length and then to select between the results. For example, determining a CRC in parallel on blocks of sixty-four bytes would require sixty-four balanced XOR trees and then selecting between the results based on the data length (e.g., the position of the last byte of data in the block of sixty-four bytes). Some deficiencies in this approach include a timing delay due to multiplexing the results, particularly as the number of bytes operated on in parallel becomes large.
Additionally, implementing such a large number of XOR trees is costly (e.g., if would require a lot of gates and silicon area in an ASIC). The number of gates and space requirements can be reduced by using ripple XOR trees of various byte widths with multiplexing to send the output of one to the input of the next appropriate XOR tree. One approach is to implement binary multiples (e.g., 1, 2, 4, 8, etc.) of input data width. However, this approach still entails significant time delays and a limited performance. Needed is a new way of generating CRC values using a multi-byte CRC generator on a variable number of bytes. SUMMARY OF THE INVENTION A device determines a cyclic redundancy check (CRC) on a block of information. A preliminary CRC on the block of information plus at least one additional byte of information is first determined.
Then, the CRC for the block of information is determined through a binary Galois field multiplier operation on the preliminary CRC. BRIEF DESCRIPTION OF THE DRAWINGS The appended claims set forth the features of the invention with particularity. The invention, together with its advantages, may be best understood from the following detailed description taken in conjunction with the accompanying drawings of which: FIG. 1A is a block diagram of an exemplary embodiment and operating environment; FIG. 1B is a block diagram of an embodiment of two components (e.g., ASICs) communicating over a link or bus; FIG.
2A is a flow diagram for determining and/or checking a CRC for a variable number of bytes of data using a binary Galois field multiplier; and FIG. 2B is a block diagram of an embodiment including a circuit for determining and/or checking a CRC for a variable ending position of a last byte of data using a balanced XOR tree followed by a binary Galois field multiplier. DETAILED DESCRIPTION Methods and apparatus are disclosed for generating and checking CRC values using a CRC generator and a binary Galois field (“GF2”) multiplier. Although embodiments are described herein for simplicity of illustration with reference to CRC-32 and its defined polynomial, the invention is not limited to CRC-32 nor any other CRC polynomial equation.
Rather, the invention is extensible to, and includes an unlimited number of CRC polynomial equations. Moreover, the methods and apparatus disclosed herein in accordance with the invention are not limited to a single computer, computing platform, operating system, router, or communications architecture, etc. Rather, the architecture and functionality taught herein are extensible to an unlimited number of systems, devices and embodiments in keeping with the scope and spirit of the invention. Embodiments described herein include various elements and limitations, with no one element or limitation contemplated as being a critical element or limitation. Each of the claims individually recite an aspect of the invention in its entirety. Moreover, some embodiments described may include, inter alia, systems, devices, methods, and computer-readable medium containing instructions.
The embodiments described herein embody various aspects and configurations within the scope and spirit of the invention. As used herein, the term “system” is used generically herein to describe any number of devices, computers, routers, networks, computer and/or communication devices or mechanisms, components or combinations thereof. The term “computer” is used generically herein to describe any number of computers, including, but not limited to personal computers, embedded processors, ASICs, chips, workstations, mainframes, etc. The term “device” is used generically herein to describe any type of mechanism, including a computer or system or component thereof. The term “process” is used generically herein to describe any type of running program, including, but not limited to a computer process, task, thread, executing application, operating system, user process, device driver, native code, machine or other language, etc., and can be interactive and/or non-interactive, executing locally and/or remotely, executing in foreground and/or background, executing in the user and/or operating address spaces, a routine of a library and/or standalone application, and is not limited to any particular memory partitioning technique. Methods and apparatus are disclosed for generating and checking CRC values using a CRC generator and a binary Galois field (“GF2”) multiplier.
These methods and apparatus could used in an unlimited number of applications and environments, such as part of computer or communications device (e.g., router or switch). The CRC generator and/or checker may be implemented singularly or in a combination of technologies, including, but not limited to, software, firmware, hardware, customized circuitry, application-specific integrated circuits, etc. A CRC generator is used to calculate a preliminary CRC value on a block of information.
This CRC generator may simultaneously operate on a single byte or on multiple bytes. In one embodiment, the CRC generator includes a balanced XOR tree which calculates the preliminary CRC value on groups of n bytes of data at a time, where n is an integer of value greater than one. For example, when data is transferred over a 512 wide bit bus, typically the value of n would be 64 (i.e., 512 bits divided by 8 bits per byte). Because the number of bytes in the data group may not be an even multiple of the value of n, one or more bytes of value zero may be appended to the data group to make it an even multiple, with the preliminary CRC being calculated on the entire appended data group. A GF2 multiplier uses the preliminary CRC value and the number of appended bytes of value zero to calculate the actual CRC value of the block of information. One embodiment assembles a GF2 multiplier with a full width polynomial divider XOR tree, and enforces zero values on the invalid tail data of a block of information, such as that corresponding to an Ethernet packet. The resultant CRC from the polynomial divider XOR tree is then compensated for the padded zero's at the end by multiplying in GF2 the CRC generated on the group of n bytes of data and padded zero's with compensating GF2 constants.
Each possible CRC value is a unique number in a GF2 counting space. Each of these numbers is represented in incrementing fashion by the following cyclic sequence for polynomial degree D (32 for CRC-32): a 0, a 1, a 2. A ((2 D )−2) In addition, multiplication of each of these by another results in an adding of exponents: a x.a y =a (x+y) When a polynomial divider is applied systematically to data which is suppressed to zero, the effect is to apply a simple multiplication of the current CRC (GF2 number) with a 1, or a (exp — crc+1) =a 1.a (exp — crc) for each bit of zero data. A byte of such zero suppressed data is expressed as: a (exp — crc+8) =a 8.a (exp — crc), and N bytes can be similarly expressed in general as: a (ply — crc) =a (exp — crc+(8.N)).=a (exp — crc) The term a (ply — crc) represents the polynomial division output CRC for data with padded zeros. Utilizing a GF2 multiplier, the effects of the padded zeros may be removed by exercising the following compensation; a (exp — crc) =a (−(8.N)).a (ply — crc) and noting that a (−(8.N)).a (8.N) =a 0=1. From the above, the implementation of this invention is a lookup table of GF2 constants a (−(8.N)) selected by N and then GF2 multiplied by the polynomial division generated CRC. 1A illustrates an exemplary embodiment and operating environment of the invention.
As shown, System A 155 is communicating over communications network 145 and links 142 and 148 with System B 105, wherein System A 155 and System B 105 include an embodiment of the invention for generating and/or checking CRC values using a multi-byte CRC generator and a GF2 multiplier on blocks of information typically having varying lengths. In one embodiment, System A 155 communications with System B 105 using Ethernet or some other protocol(s), and using a CRC, such as, but not limited to, CRC-8, CRC-10, CRC-12, CRC-16, CRC-CCITT, CRC-32, or some other CRC polynomial to detect errors. Various embodiments of System A 155 and/or System B 105 include, but are not limited to, an interface component (e.g., a network card) of a larger system or the larger system itself, such as a computer, switch, router or other device.
System A 155 and System B 105 may be a part of the same or different devices. The CRC may be generated by processor 110 and/or 160, and/or within network interface 141 and/or 149.
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